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mosel vitelic 1 v53c8256h ultra-high speed, 256k x 8 fast page mode cmos dynamic ram preliminary v53c8256h rev. 1.2 july 1997 high performance 35 40 45 50 max. ras access time, (t rac ) 35 ns 40 ns 45 ns 50 ns max. column address access time, (t caa ) 18 ns 20 ns 22 ns 24 ns min. fast page mode cycle time, (t pc ) 21 ns 23 ns 25 ns 28 ns min. read/write cycle time, (t rc ) 70 ns 75 ns 80 ns 90 ns features n 256k x 8-bit organization n fast page mode for a sustained data rate of 47 mhz n ras access time: 35, 40, 45, 50 ns n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh capability n refresh interval: 512 cycles/8 ms n single 5v 10% power supply n available in 24-pin 300 mil plastic dip, 26/24-pin 300 mil soj, and 28-pin tsop-i packages description the v53c8256h is a high speed 262,144 x 8 bit cmos dynamic random access memory. the v53c8256h offers a combination of features: fast page mode for high data bandwidth, fast usable speed, cmos standby current. all inputs and outputs are ttl compatible. input and output capacitances are significantly lowered to allow increased system performance. fast page mode operation allows random access of up to 512 (x8) bits within a row with cycle times as short as 21 ns. because of static circuitry, the cas clock is not in the critical timing path. the flow-through column address latches allow address pipelining while re- laxing many critical system timing requirements for fast usable speed. these features make the v53c8256h ideally suited for graphics, digital sig- nal processing and high performance computing systems. device usage chart operating temperature range package outline access time (ns) power temperature mark p k t 50 60 70 std. 0 c to 70 c blank
2 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 family device pkg (t rac ) speed pwr. v53c 256 35 (35 ns) 40 (40 ns) 45 (45 ns) 50 (50 ns) temp. blank (0 c to 70 c) blank (normal) k (soj) t (tsop-i) 8256h-01 p (plastic dip) h 8 24-pin plastic dip pin configuration top view 28-pin tsop-i pin configuration top view 26/24-pin soj pin configuration top view pin names vss i/o1 i/o2 i/o3 i/o4 we ras a0 a1 a2 vss i/o8 i/o7 i/o6 i/o5 cas oe a8 a7 a6 8256h-02 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 a3 vdd a5 a4 11 12 14 13 a 0 ? 8 address inputs ras row address strobe cas column address strobe we write enable oe output enable i/o 1 ?/o 8 data input, output v dd +5v supply v ss 0v supply nc no connect vss i/o1 i/o2 i/o3 i/o4 we ras a0 a1 a2 vss i/o8 i/o7 i/o6 i/o5 cas oe a8 a7 a6 8256h-03 1 2 3 4 5 6 8 9 10 11 27 26 24 23 22 21 19 18 17 16 a3 vdd a5 a4 12 13 15 14 description pkg. pin count plastic dip p 24 soj k 26/24 tsop-i t 28
mosel vitelic v53c8256h 3 v53c8256h rev. 1.2 july 1997 absolute maximum ratings* ambient temperature under bias .............................. ?0 c to +80 c storage temperature (plastic) ...... -55 c to +125 c voltage relative to v ss ...................?.0v to +7.0v data output current ..................................... 50 ma power dissipation .......................................... 1.0 w * note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v dd = 5 v 10%, v ss = 0 v *note: capacitance is sampled and not 100% tested. symbol parameter min. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 45pf c out data input/output 5 7 pf block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v dd v ss 9 8256h-05 i/o 1 address buffers and predecoders x 0 -x row decoders 512 memory array column decoders data i/o bus y 0 -y 8 512 x 8 i/o buffer i/o 2 i/o 3 i/o 4 oe clock generator we clock generator cas clock generator 256k x 8 ras clock generator oe we cas ras ? ? 8 i/o 5 i/o 6 i/o 7 i/o 8
4 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0 v, unless otherwise specified. symbol parameter access time v53c8256h unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m av ss v in v cc i lo output leakage current (for high-z state) ?0 10 m av ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 35 160 ma t rc = t rc (min.) 1, 2 40 150 45 145 50 135 i cc2 v cc supply current, ttl standby 4 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 35 160 ma t rc = t rc (min.) 2 40 150 45 145 50 135 i cc4 v cc supply current, fast page mode operation 35 95 ma minimum cycle 1, 2 40 90 45 85 50 80 i cc5 v cc supply current, standby, output enabled 2 ma ras = v ih , cas = v il , other inputs 3 v ss 1 i cc6 vcc supply current, cmos standby 1 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc + 1 v 3 v ol output low voltage 0.4 v i ol = 4.2 ma v oh output high voltage 2.4 v i oh = ? ma
5 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 ac characteristics t a = 0 c to 70 c, v cc = 5 v 10%, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # jedec symbol symbol parameter 35 40 45 50 unit notes min. max. min. max. min. max. min. max. 1t rl1rh1 t ras ras pulse width 35 75k 40 75k 45 75k 50 75k ns 2t rl2rl2 t rc read or write cycle time 70 75 80 90 ns 3t rh2rl2 t rp ras precharge time 25 25 25 30 ns 4t rl1ch1 t csh cas hold time 35 40 45 50 ns 5t cl1ch1 t cas cas pulse width 12 12 13 14 ns 6t rl1cl1 t rcd ras to cas delay 16 23 17 28 18 32 19 36 ns 7t wh2cl2 t rcs read command setup time 0000ns4 8t avrl2 t asr row address setup time 0000ns 9t rl1ax t rah row address hold time 6789ns 10 t avcl2 t asc column address setup time 0000ns 11 t cl1ax t cah column address hold time 4567ns 12 t cl1rh1(r) t rsh (r) ras hold time (read cycle) 12 12 13 14 ns 13 t ch2rl2 t crp cas to ras precharge time 5555ns 14 t ch2wx t rch read command hold time referenced to cas 0000ns5 15 t rh2wx t rrh read command hold time referenced to ras 0000ns5 16 t oel1rh2 t roh ras hold time referenced to oe 8 8 9 10 ns 17 t gl1qv t oac access time from oe 12 12 13 14 ns 18 t cl1qv t cac access time from cas 12 12 13 14 ns 6, 7 19 t rl1qv t rac access time from ras 35 40 45 50 ns 6, 8, 9 20 t avqv t caa access time from column address 18 20 22 24 ns 6, 7, 10 21 t cl1qx t lz oe or cas to low-z output 0000ns16 22 t ch2qz t hz oe or cas to high-z output 06060708ns16 23 t rl1ax t ar column address hold time from ras 28 30 35 40 ns 24 t rl1av t rad ras to column address delay time 11 17 12 20 13 23 14 26 ns 11 25 t cl1rh1(w) t rsh (w) ras or cas hold time in write cycle 12 12 13 14 ns 26 t wl1ch1 t cwl write command to cas lead time 12 12 13 14 ns 27 t wl1cl2 t wcs write command setup time 0000ns 12, 13 28 t cl1wh1 t wch write command hold time 5567ns
6 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h 29 t wl1wh1 t wp write pulse width 5567ns 30 t rl1wh1 t wcr write command hold time from ras 28 30 35 40 ns 31 t wl1rh1 t rwl write command to ras lead time 12 12 13 14 ns 32 t dvwl2 t ds data in setup time 0000ns14 33 t wl1dx t dh data in hold time 4567ns14 34 t wl1gl2 t woh write to oe hold time 5678ns14 35 t gh2dx t oed oe to data delay time 5678ns14 36 t rl2rl2 (rmw) t rwc read-modify-write cycle time 105 110 115 130 ns 37 t rl1rh1 (rmw) t rrw read-modify-write cycle ras pulse width 70 75 80 87 ns 38 t cl1wl2 t cwd cas to we delay 28 30 32 34 ns 12 39 t rl1wl2 t rwd ras to we delay in read- modify-write cycle 54 58 62 68 ns 12 40 t cl1ch1 t crw cas pulse width (rmw) 46 48 50 52 ns 41 t avwl2 t awd col. address to we delay 35 38 41 42 ns 12 42 t cl2cl2 t pc fast page mode 21 23 25 28 ns read or write cycle time 43 t ch2cl2 t cp cas precharge time 4567ns 44 t avrh1 t car column address to ras setup time 18 20 22 24 ns 45 t ch2qv t cap access time from column precharge 20 22 24 27 ns 7 46 t rl1dx t dhr data in hold time referenced to ras 28 30 35 40 ns 47 t cl1rl2 t csr cas setup time cas -before-ras refresh 10 10 10 10 ns 48 t rh2cl2 t rpc ras to cas precharge time 0000ns 49 t rl1ch1 t chr cas hold time cas -before-ras refresh 8 8 10 12 ns 50 t cl2cl2 (rmw) t pcm fast page mode read-modify- write cycle time 58 60 65 70 ns t t t t transition time (rise and fall) 3 50 3 50 3 50 3 50 ns 15 t ref refresh interval (512 cycles) 8888ms17 # jedec symbol symbol parameter 35 40 45 50 unit notes min. max. min. max. min. max. min. max. ac characteristics (cont?)
7 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i cc (max.) is measured with a maximum of two transitions per address cycle in fast page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to ?.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to two ttl inputs and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad ex- ceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
8 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h waveforms of read cycle waveforms of early write cycle ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (8) t crp (13) t cah (11) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t roh (15) t car (44) t caa (20) t cac (18) t t hz (22) t lz (21) ih v il v we oh v ol v i/o 8256h-06 valid data-out address rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16) ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (11) t t rad (24) t rah (9) t asr (8) t t wcr (30) t rwl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 8256h-07 t t cwl (26) wch (28) t t ds (32) column address valid data-in high-z ras cas we oe i/o address t car (44) asc (10) wcs (27) wp (29) row address don? care undefined
9 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 waveforms of write cycle (oe controlled write) waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (11) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 8256h-09 valid data-in t ds (32) t rad (24) ras cas we oe i/o t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) rwl (31) t cwl (26) t column address row address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (11) t asc (10) t rah (9) t asr (8) wp (29) rwl (31) t oed (35) t ih v il v ih v il v ih v il v 8256h-09 valid data-out t rac (19) t cwl (26) t t rad (24) t t oac (17) t t dh (33) t ds (32) hz (22) cac (18) t lz (21) valid data-in ih v il v oh ol ras cas we oe i/o address t rwc (36) t rrw (37) t ar (23) t csh (4) t rsh (w)(25) t crw (40) t rwd (39) cwd (38) t awd (41) t t caa (20) don? care undefined
10 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h waveforms of fast page mode read cycle waveforms of fast page mode write cycle valid data out valid data out column address cac (18) t t hz (22) hz (22) hz (22) hz (22) row address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 8256h-10 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (11) t hz (22) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (11) t rcs (7) t rcs (7) t rch (14) t oac (17) t t t oac (17) t caa (20) t rrh (15) t hz (22) lz (21) t rac (19) t t cac (18) valid data out t crp (13) t t lz (21) t ras cas we oe i/o address t asc (10) t lz (21) cac (18) t caa (20) oac (17) cap (45) t cah (11) row add ih v il v ih v il v ih v il v ih v il v t t asr (8) 8256h-11 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) valid data in t crp (13) t wcs (27) wp (29) t cah (11) t asc (10) t cah (11) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t valid data in t dh (33) t ds (32) valid data in t dh (33) t ds (32) t rp (3) t ar (23) ras cas we oe i/o address open open t rwl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) don? care undefined
11 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 waveforms of fast page mode read-write cycle waveforms of ras only refresh cycle row add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address 8256h-12 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (w)(25) column address t cah (11) t cas (5) t cas (5) t t t crp (13) t rcs (7) t cah (11) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t rwl (31) t awd (41) t caa (20) t t oac (17) t awd (41) t oac (17) in t cac (18) t oed (35) t ds (32) t dh (33) t lz (21) in out hz (22) t oed (35) ds (32) t dh (33) t t t t cac (18) t caa (20) lz (21) in hz (22) t oed (35) ds (32) t dh (33) t t t cac (18) t caa (20) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras cas we oe i/o address t awd (41) out rac (19) t oac (17) t rwd (39) cah (11) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out cap (45) cap (45) ih v il v ras ih v il v rp (3) t ih v il v cas t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 8256h-13 we, oe = don? care note: address row addr don? care undefined
12 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h waveforms of cas -before-ras refresh counter test cycle waveforms of cas -before-ras refresh cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 8256h-14 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t dh (33) t cp (43) t cas (5) t rch (14) t rrh (15) t roh (16) t oac (17) t hz (22) t hz (22) t r wl (31) t cwl (26) t ds (32) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) i/o address we we i/o d out d in ras cas oe oe i/o ih v il v ras oh v ol v ih v il v cas t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) rp (3) t t rpc (48) t chr (49) rp (3) t note: we, oe, a 0 ? 7 = don? care 8256h-15 don? care undefined
13 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 8256h-16 t chr (49) t rad (24) t asc (10) t t cah (11) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas we oe i/o address valid data rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 8256h-17 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (11) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v valid data-in t dhr (46) t rc (2) ras cas we oe i/o address t dh (33) don? care undefined
14 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 functional description the v53c8256h is a cmos dynamic ram opti- mized for high data bandwidth, low power applica- tions. it is functionally similar to a traditional dynamic ram. the v53c8256h reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. the row address is latched by the row address strobe (ras ). the col- umn address ?lows through?an internal address buffer and is latched by the column address strobe (cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be end- ed or aborted before the minimum t ras time has ex- pired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable (we ) signal high during a ras /cas opera- tion. the column address must be held for a mini- mum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for exam- ple, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column ad- dress is latched by cas . the write cycle can be we controlled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas - controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied. refresh cycle to retain data, 512 refresh cycles are required in each 8 ms period. there are two ways to refresh the memory: 1. by clocking each of the 512 row addresses (a 0 through a 8 ) with ras at least once every 8 ms. any read, write, read-modify-write or ras - only cycle refreshes the addressed row. 2. using a cas -before-ras refresh cycle. if cas makes a transition from low to high to low after the previous cycle and before ras falls, cas - before-ras refresh is activated. the v53c8256h uses the output of an internal 9-bit counter as the source of row addresses and ig- nore external address inputs. cas -before-ras is a ?efresh-only?mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cy- cle. a cas -before-ras counter test mode is provid- ed to ensure reliable operation of the internal refresh counter. fast page mode operation fast page mode operation permits all 512 col- umns within a selected row of the device to be ran- domly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to reapply it for each cycle. the column ad- dress buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occurrence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer and acts as an output enable. during fast page mode opera- tion, read, write, read-modify-write or read- write-read cycles are possible at random address- es within a row. following the initial entry cycle into fast page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column address is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output.
mosel vitelic v53c8256h 15 v53c8256h rev. 1.2 july 1997 fast page mode provides a sustained data rate of 47 mhz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: data output operation the v53c8256h input/output is controlled by oe , cas , we and ras . a ras low transition en- ables the transfer of data to and from the selected row address in the memory array. a ras high tran- sition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level dis- ables the i/o path and the output driver if it is en- abled. a cas low transition while ras is high has no effect on the i/o data path or on the output driv- ers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latch- es. a we low level can also disable the output driv- ers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is neces- sary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v dd supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v dd current requirement of the v53c8256h is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i dd will exhibit current transients. it is recommended that ras and cas track with v dd or be held at a valid v ih during power-on to avoid current surges. table 1. v53c8256h data output operation for various cycle types data rate 512 t rc 511 t pc + ---------------------------------------- = cycle type i/o state read cycles data from addressed memory cell cas -controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell fast page mode read cycle data from addressed memory cell fast page mode write cycle (early write) high-z fast page mode read- modify-write cycle data from addressed memory cell ras -only refresh high-z cas -before-ras refresh cycle data remains as in previous cycle cas -only cycles high-z
16 v53c8256h rev. 1.2 july 1997 mosel vitelic v53c8256h package diagrams 24-pin 300 mil pdip 26/24-pin 300 mil soj 1.310 max. [33.27 max.] 0.048 ?0.065 [1.22 ?1.65] 0.018 ?0.024 [0.457 ?0.610] .180 max. [4.57 max.] 0.005 0.050 [0.127 ?1.27] .100 typ. [2.54 typ.] .008 ?.013 [.203 ?.330] 0.300 ?0.330 [7.62 ?8.38] 0.250 ?0.300 [6.35 ?7.62] 0.320 ?0.390 [8.13 ?9.91] 0.110 ?0.140 [2.79 ?3.56] unit in inches [mm] 0.05 typ. [1.27 typ.] 0.018 typ. [0.457 typ.] 0.665 ?0.698 [16.89 ?17.73] 0.025 min. [0.635 min.] 0.125 ?0.135 [3.175 ?3.429] 0.028 typ. [0.711 typ.] 0.332 ?0.342 [8.43 ?8.69] unit in inches [mm] 0.296 ?0.304 [7.52 ?7.72] 0.255 ?0.275 [6.477 ?6.985] 0.082 ?0.093 [2.08 ?2.36]
17 mosel vitelic v53c8256h v53c8256h rev. 1.2 july 1997 28-pin tsop-i detail ? .520 ?.535 [13.21 ?13.59] .035 ?.043 [.889 ?1.09] .035 ?.043 [.889 ?1.09] .311 ?.319 [7.90 ?8.10] unit in inches [mm] .037 ?.041 [.940 ?1.04] .020 ?.028 [.508 ?.711] 0 ?6 .004 ?.008 [.102 ?.203] d d .007 ?.009 [.178 ?.229] .007 ?.011 [.178 ?.279] .004 ?.006 [.102 ?.152] base metal with plating .008 ?.20 [.203 ?5.08] .055 ?.063 [1.40 1.60] .055 ?.063 [1.40 1.60] .055 ?.063 [1.40 1.60] .012 max [.305 max] .000 .0102 0.25 bsc [6.35 bsc] gage plane .55 [13.97] .039 dia. [.991 dia] see detail ? top view bottom view see detail ? detail ? detail ? section ?-d .047 [1.19] .002 ?.006 [.051 ?.152] 2.01 dia. x .000 .0004 .079 dia. x deep deep fixed pin (1 plcs.) 0.10 [2.54] 0.10 (.004) [2.54 (.102)] 0.10 [2.54] 0.25 [6.35] .461 ?.469 [11.71 ?11.91]
mosel vitelic worldwide offices v53c8256h u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan rm.302 annex-g higashi-nakano nakano-ku, tokyo 164 phone: 011-81-03-3365-2851 fax: 011-81-03-3365-2836 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 310-498-3314 fax: 310-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?copyright 1997, mosel vitelic inc. 7/97 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 u.s. sales offices

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